Modern processors are required to execute complex tasks at very high speeds. The introduction of pipelined processor architectures improved the performances of modern processors but also introduced some problems. In a pipelined architecture an execution of an instruction is split to multiple stages. The PowerPC™ processors family of Freescale Semiconductor, Inc. is an example of pipelined processors.
Pipelined processors experience stalls. A stall occurs when an execution of a current instruction depends upon information that is not ready on time.
One method for reducing the amount of stalls and alternatively or optionally decreases the duration of stalls is to perform feed-forwarding. Feed-forwarding usually involves retrieving information before it is sent to a register file. In many cases processed information is both fetched to one of the pipelined units of the processor and in also sent (written-back) to the register file.
Various prior art processors are capable of performing simple feed-forwarding operations. A simple feed-forward operation involves one target register and one source register. Some prior art processors and methods for simple feed-forwarding operations are illustrated in U.S. Pat. No. 6,901,504 of Luick and in U.S. Pat. No. 6,145,097 of Moyer et al., both being incorporated herein by reference.
There is a need to provide an efficient method and device for performing complex feed forward operations.